模六计数器的VHDL程序怎么编
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解决时间 2021-01-10 06:25
- 提问者网友：未信
- 2021-01-09 20:20
模六计数器的VHDL程序怎么编
最佳答案
- 二级知识专家网友：往事隔山水
- 2021-01-09 20:31
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity test is
PORT (
clk,clrn:in std_logic;
dataout: out integer range 0 to 5
);
end test;
architecture ONE of test is
signal q:integer range 0 to 5;
begin
process (clk,clrn)
begin
if clrn='0' then
q<=0;
elsif clk'event and clk='1' then
if q=5 then
q<=0;
else
q<=q+1;
end if;
end if;
end process ;
dataout<=q;
end ONE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity test is
PORT (
clk,clrn:in std_logic;
dataout: out integer range 0 to 5
);
end test;
architecture ONE of test is
signal q:integer range 0 to 5;
begin
process (clk,clrn)
begin
if clrn='0' then
q<=0;
elsif clk'event and clk='1' then
if q=5 then
q<=0;
else
q<=q+1;
end if;
end if;
end process ;
dataout<=q;
end ONE;
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