求基于FPGA器件的4*4位乘法器的实现

求基于FPGA器件的4*4位乘法器的实现

如果不用IP Core，自己做的话，可以用循环叠加来做，就象你用手算一样。
A3 A2 A1 A0
x)B3 B2 B1 B0
---------------------------------
A3 A2 A1 A0 （B0=1时，为A3 A2 A1 A0；B0=0时，这一行全0）
A3 A2 A1 A0
A3 A2 A1 A0
A3 A2 A1 A0
---------------------------------
相加得结果

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity Multiplier is
generic (
DATA_WIDTH : natural := 4
);
port (
reset_n : in std_logic;
clk : in std_logic;
InputX : in std_logic_vector(DATA_WIDTH-1 downto 0);
InputY : in std_logic_vector(DATA_WIDTH-1 downto 0);
Cal : in std_logic;
Result : out std_logic_vector(DATA_WIDTH*2-1 downto 0)
);
end Multiplier;

architecture Multiplier_arch of Multiplier is

type MUL_DATA_ARRAY_TYPE is array (DATA_WIDTH-1 downto 0) of std_logic_vector(DATA_WIDTH*2-1 downto 0);
signal mulDataArray : MUL_DATA_ARRAY_TYPE;

begin
mulDataArray_gen : for I in 0 to DATA_WIDTH-1 generate
mulDataArray(I)(DATA_WIDTH*2-1 downto DATA_WIDTH+I) <= (others => '0');
mulDataArray(I)(DATA_WIDTH+I-1 downto I) <= InputX when InputY(I) = '1' else (others => '0');
mulDataArray(I)(I-1 downto 0) <= (others => '0');
end generate;

process(reset_n, clk)
variable resultTmp : std_logic_vector(DATA_WIDTH*2-1 downto 0);
begin
if reset_n = '0' then
Result <= (others => '0');
elsif rising_edge(clk) then
resultTmp := mulDataArray(0);
for I in 1 to DATA_WIDTH-1 loop
resultTmp := resultTmp + mulDataArray(I);
end loop;
if Cal = '1' then
Result <= resultTmp;
end if;
end if;
end process;

end Multiplier_arch;

价格好说，多少钱？