FPGA编译错误

Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 11.0 Build 157 04/27/2011 SJ Full Version
Info: Processing started: Wed Dec 11 12:32:12 2013
Info: Version 11.0 Build 157 04/27/2011 SJ Full Version
Info: Processing started: Wed Dec 11 12:32:12 2013
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off rd -c rd
Info: Parallel compilation is enabled and will use 2 of the 2 processors detected
Info: Found 1 design units, including 1 entities, in source file /altera/lichen/lic/led_water/rd.v
Info: Found entity 1: led_light
Info: Found entity 1: led_light
Error (10228): Verilog HDL error at led_light.v(1): module "led_light" cannot be declared more than once
Info (10499): HDL info at rd.v(1): see declaration for object "led_light"
Info: Found 0 design units, including 0 entities, in source file /altera/lichen/lic/led_water/led_light.v
Error: Quartus II Analysis & Synthesis was unsuccessful. 1 error, 0 warnings
Error: Peak virtual memory: 254 megabytes
Error: Processing ended: Wed Dec 11 12:32:12 2013
Error: Elapsed time: 00:00:00
Error: Total CPU time (on all processors): 00:00:01
Error: Peak virtual memory: 254 megabytes
Error: Processing ended: Wed Dec 11 12:32:12 2013
Error: Elapsed time: 00:00:00
Error: Total CPU time (on all processors): 00:00:01
Error: Quartus II Full Compilation was unsuccessful. 3 errors, 0 warnings

怎么处理
附上代码{

module led_light(led);
output[3:0] led;
assign led=3'b10;
endmodule
}

Error (10228): Verilog HDL error at led_light.v(1): module "led_light" cannot be declared more than once

你在这个工程里建立了不止一个名为led_light的.v文件应该，你在工程里查看修改一下应该就行了，而且你的 assign led=3‘b10；也应该是个warning 3bit的数至少应该是 led=3’b010;

数字电路基础有待加强； led_light模块，没有clk信号，没有任何输入，若果是非时序电路，也应该有输入，不然的话，直接把响应的信号接地或者VCC

从错误报告上来看，应该是led_light被申明了两次。 楼上说的不对，模块是可以没有输入的，没有输入的模块就相当于直接把输出接地或者接电源。