FPGA采集多路温度，买了一块FPGA开发板，芯片EP1C3T144C8.温度传感器用DS18B20，Verilog编程怎么写，求助

FPGA采集多路温度，买了一块FPGA开发板，芯片EP1C3T144C8.温度传感器用DS18B20，Verilog编程怎么写，求助

其实很简单，先看硬件原理图，弄懂信号流向。再看DS18B20的数据手册(Datasheet)，注意建立时间和保持时间（以防后面需要做时序约束）。然后看DS18B20各个功能的时序图。严格控制FPGA按照时序图与DS18B20通信。你只需模仿出主机方（HOST)的时序即可，设备方(Device)时序图即为DS18B20通信时序。只要注意好信号的读写方向（一般是用TRI控制信号流向），写个FSM状态机就很随意的完成基本的通信了。

三根线， 温度传感器用DS18B20 quartusII软件 编程。 再看看别人怎么说的。

Verilog编程，quartusII软件，知道开发板对应硬件接口就可以啦

第一个文件：ds18b20.v `timescale 1ns / 1ps module ds18b20 ( clk, chipselect, read_n, //input readdata, //output dio ); //inout input clk, chipselect, read_n; output [15:0] readdata; inout dio; reg [31:0] ro=32'hbecc44cc; reg [15:0] ri; reg [15:0] pout; reg [ 5:0] count; reg [12:0] cnt; reg dout; wire clk781_25khz; assign clk781_25khz=count[5]; always @(posedge clk) count<=count+1'b1; always @(posedge clk781_25khz) cnt<=cnt+1'b1; always @(posedge cnt[12]) pout<=ri; assign readdata=(chipselect & ~read_n)? pout : 16'b0; reg reset,lo, hi,rd; always @(posedge cnt[0]) reset<=cnt[12]|cnt[10]|cnt[9]; always @(posedge cnt[0]) lo <=|cnt[5:1] | ~cnt[10]; always @(posedge cnt[0]) hi <=&cnt[5:1] | ~cnt[10]; always @(posedge cnt[0]) rd <=cnt[3]|cnt[4]|cnt[5]|~cnt[10]|cnt[11]|~cnt[12]; always @(negedge lo or posedge cnt[12]) if (cnt[12]==1) ro<=32'hbecc44cc; else {ro[30:0],dout} <= ro; always @(posedge rd) ri <= {dio,ri[15:1]}; assign dio=reset&(hi|(lo&dout))?1'bz:1'b0; endmodule 第二个文件：ds18b20_hw.tcl # TCL File Generated by Component Editor 11.0 # Mon Dec 12 00:54:43 CST 2011 # DO NOT MODIFY # +----------------------------------- # | # | ds18b20 "ds18b20" v1.0 # | null 2011.12.12.00:54:43 # | # | # | D:/myip11/ds18b20.v # | # | ./ds18b20.v syn, sim # | # +----------------------------------- # +----------------------------------- # | request TCL package from ACDS 11.0 # | package require -exact sopc 11.0 # | # +----------------------------------- # +----------------------------------- # | module ds18b20 # | set_module_property NAME ds18b20 set_module_property VERSION 1.0 set_module_property INTERNAL false set_module_property OPAQUE_ADDRESS_MAP true set_module_property DISPLAY_NAME ds18b20 set_module_property TOP_LEVEL_HDL_FILE ds18b20.v set_module_property TOP_LEVEL_HDL_MODULE ds18b20 set_module_property INSTANTIATE_IN_SYSTEM_MODULE true set_module_property EDITABLE true set_module_property ANALYZE_HDL TRUE set_module_property STATIC_TOP_LEVEL_MODULE_NAME "ds18b20" set_module_property FIX_110_VIP_PATH false # | # +----------------------------------- # +----------------------------------- # | files # | add_file ds18b20.v {SYNTHESIS SIMULATION} # | # +----------------------------------- # +----------------------------------- # | parameters # | # | # +----------------------------------- # +----------------------------------- # | display items # | # | # +----------------------------------- # +----------------------------------- # | connection point clock # | add_interface clock clock end set_interface_property clock clockRate 0 set_interface_property clock ENABLED true add_interface_port clock clk clk Input 1 # | # +----------------------------------- # +----------------------------------- # | connection point avalon_slave_0 # | add_interface avalon_slave_0 avalon end set_interface_property avalon_slave_0 addressAlignment NATIVE set_interface_property avalon_slave_0 addressUnits WORDS set_interface_property avalon_slave_0 associatedClock clock set_interface_property avalon_slave_0 associatedReset clock_reset set_interface_property avalon_slave_0 burstOnBurstBoundariesOnly false set_interface_property avalon_slave_0 explicitAddressSpan 0 set_interface_property avalon_slave_0 holdTime 0 set_interface_property avalon_slave_0 isMemoryDevice false set_interface_property avalon_slave_0 isNonVolatileStorage false set_interface_property avalon_slave_0 linewrapBursts false set_interface_property avalon_slave_0 maximumPendingReadTransactions 0 set_interface_property avalon_slave_0 printableDevice false set_interface_property avalon_slave_0 readLatency 0 set_interface_property avalon_slave_0 readWaitTime 1 set_interface_property avalon_slave_0 setupTime 0 set_interface_property avalon_slave_0 timingUnits Cycles set_interface_property avalon_slave_0 writeWaitTime 0 set_interface_property avalon_slave_0 ENABLED true add_interface_port avalon_slave_0 chipselect chipselect Input 1 add_interface_port avalon_slave_0 read_n read_n Input 1 add_interface_port avalon_slave_0 readdata readdata Output 16 # | # +----------------------------------- # +----------------------------------- # | connection point conduit_end # | add_interface conduit_end conduit end set_interface_property conduit_end ENABLED true add_interface_port conduit_end dio export Bidir 1 # | # +----------------------------------- 以上两个文件均在quartus 11中完成，成文DS18B20一个IP. 接下来：将本IP挂接到阿瓦龙总线上，直接读取16位的整数，再根据数据手册把温度翻译为可理解的内容即可。