Error (10500): VHDL syntax error at FB_ADDER.vhd(31) near text ";"; expecting "<=&

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY FB_ADDER IS
PORT (CLK1: IN STD_LOGIC;
A, B : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
S : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
COUT : OUT STD_LOGIC);
END ENTITY FB_ADDER;
ARCHITECTURE add4 OF FB_ADDER IS
COMPONENT DFF4
PORT (CLK : IN STD_LOGIC;
D : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
Q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0));
END COMPONENT ;
COMPONENT adder4
PORT (cin : IN STD_LOGIC;
a, b : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
s : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
Cout : OUT STD_LOGIC);
END COMPONENT ;
COMPONENT DFF1
PORT (CLK, D : IN STD_LOGIC;
Q : OUT STD_LOGIC);
END COMPONENT ;
SIGNAL ai, bi, soi : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL cou :STD_LOGIC;
BEGIN
u1 : DFF4 PORT MAP(D=>A,Q=>ai,CLK=>CLK1);
u2 : DFF4 PORT MAP(D=>B,Q=>bi,CLK=>CLK1);
u3 : DFF4 PORT MAP(D=>soi,Q=>S,CLK=>CLK1);
u4 ：adder4 PORT MAP(cin<='0',a=>ai,b=>bi,s=>soi,Cout=>cou);
u5 : DFF1 PORT MAP(D=>cou,Q=>COUT,CLK=>CLK1 );
END ARCHITECTURE add4;

Error (10500): VHDL syntax error at FB_ADDER.vhd(31) near text ?
Error (10500): VHDL syntax error at FB_ADDER.vhd(31) near text "?; expecting "(", or "'", or "."
Error (10500): VHDL syntax error at FB_ADDER.vhd(31) near text ?
Error (10500): VHDL syntax error at FB_ADDER.vhd(31) near text ";"; expecting "<="

这一句有错误：u4 : adder4 PORT MAP(cin<='0',a=>ai,b=>bi,s=>soi,Cout=>cou);

你需要在结构体开始的地方声明一个信号，例如signal GND:std_logic;，然后在结构体中给GND赋值，GND <= '0';，最后将上面出错的一句改成u4 : adder4 PORT MAP(cin => GND, a => ai, b=>bi, s=>soi,Cout=>cou);。

提示信息为语法错误： 变量的赋值才用 := 信号的赋值用 <= 应该就是这个错误！具体要看你的代码怎么写的，建议好好看看vhdl语法！