帮忙做个基于Vhdl的音乐播放器，eda的，要求是有开始和结束，能选歌，两首就够了

帮忙做个基于Vhdl的音乐播放器，eda的，要求是有开始和结束，能选歌，两首就够了

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY songer IS
PORT(clk12mhz:IN STD_LOGIC;
clk8hz,done,COUT:IN STD_LOGIC;
code1:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
HIGH1:OUT STD_LOGIC;
spkout:OUT STD_LOGIC);
END songer;
architecture one of songer is
COMPONENT notetabs
PORT (clk:IN STD_LOGIC;
toneindex:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END COMPONENT;

COMPONENT tonetaba
PORT (done,COUT:in STD_LOGIC;
index:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
code:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
high:out STD_LOGIC;
tone:OUT STD_LOGIC_VECTOR(10 DOWNTO 0));
END COMPONENT;

COMPONENT speakera
PORT (clk:IN STD_LOGIC;
done,COUT:IN STD_LOGIC;
tone:IN STD_LOGIC_VECTOR(10 DOWNTO 0);
SPKS:out STD_LOGIC);
END COMPONENT;

SIGNAL tone:STD_LOGIC_VECTOR(10 DOWNTO 0);
SIGNAL toneindex:STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
U1:notetabs PORT MAP(clk=>clk8hz,toneindex=>toneindex);
u2:tonetaba PORT MAP(index=>toneindex,tone=>tone,code=>code1,high=>high1,DONE=>DONE,cout=>cout);
u3:speakera PORT MAP(clk=>clk12mhz,done=>done,COUT=>COUT,tone=>tone,spks=>spkout);
END;

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY notetabs IS
PORT(clk:IN STD_LOGIC;
toneindex:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END;
ARCHITECTURE one OF notetabs IS
COMPONENT music
PORT(address:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
clock:IN STD_LOGIC;
Q:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END COMPONENT;
SIGNAL counter:STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
CNT8:PROCESS(clk,counter)
begin

IF counter=138 THEN counter<="00000000";
ELSIF(clk'EVENT AND clk='1')then
counter<=counter+1;
END IF;

END process;

END;

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY tonetaba IS
PORT(done,COUT:in STD_LOGIC;
index:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
code:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
HIGH:OUT STD_LOGIC;
tone:OUT STD_LOGIC_VECTOR(10 DOWNTO 0));
END tonetaba;
architecture one OF tonetaba IS
BEGIN
search:PROCESS(index)
BEGIN
if done='1'OR COUT='1' THEN
CASE index IS
WHEN"0000"=>tone<="11111111111";code<="0000";high<='0';
WHEN"0001"=>tone<="01100000101";code<="0001";high<='0';
WHEN"0010"=>tone<="01110010000";code<="0010";high<='0';
WHEN"0011"=>tone<="10000001100";code<="0011";high<='0';
WHEN"0101"=>tone<="10010101101";code<="0101";high<='0';
WHEN"0110"=>tone<="10100001010";code<="0110";high<='0';
WHEN"0111"=>tone<="10101011100";code<="0111";high<='0';
WHEN"1000"=>tone<="10110000010";code<="0001";high<='1';
WHEN"1001"=>tone<="10111001000";code<="0010";high<='1';
WHEN"1010"=>tone<="11000000110";code<="0011";high<='1';
WHEN"1100"=>tone<="11001010110";code<="0101";high<='1';
WHEN"1101"=>tone<="11010000100";code<="0110";high<='1';
WHEN"1111"=>tone<="11011000000";code<="0001";high<='1';
WHEN OTHERS=>NULL;
END CASE;
END IF;
END PROCESS;
END ONE;

-数控频率转换器
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY speakera IS
PORT( clk:IN STD_LOGIC;
done,COUT:IN STD_LOGIC;
tone:IN STD_LOGIC_VECTOR(10 DOWNTO 0);
SPKS:OUT STD_LOGIC);
END speakera;
ARCHITECTURE one OF speakera is
SIGNAL preclk,fullspks:STD_LOGIC;
BEGIN
divideclk:process(clk)
VARIABLE count4:STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN

IF count4>11 THEN
preclk<='1';
count4:="0000";
ELSIF clk'EVENT AND clk='1' THEN
count4:=count4+1;preclk<='0';
END IF;
END PROCESS;
genspks:PROCESS(preclk,tone)
VARIABLE count11:STD_LOGIC_VECTOR(10 DOWNTO 0);
BEGIN
IF done='1'OR COUT='1' THEN
IF preclk'EVENT AND preclk='1' THEN
IF count11=16#7FF# THEN count11:=tone;
fullspks<='1';
ELSE
count11:=count11+1;
fullspks<='0';
END IF;
END IF;
END IF;
END PROCESS;
delayspks: PROCESS(fullspks)
VARIABLE count2:STD_LOGIC;
BEGIN
IF fullspks'EVENT AND fullspks='1' then
count2:=NOT count2;
if count2='1' THEN spks<='1';
ELSE
spks<='0';
END IF;
END IF;
END PROCESS;
END ONE;

然后自己定制一个RAM

做好这道题的一定是超级牛人，月薪绝对不低于20w！
1>要会文件系统；
2>要会设计CPU(借用免费的也行)；
3>要会编写操作体统(借用免费的也行)；
4>要会解压MP3格式的应用程序；
5>还得上缴MP3的许可费；
6>要会xHDL；
7>会仿真(ModelSim之类的)......
----
你想20分打发？幻想、妄想、遐想、瞎想...整个百度的分都不够！
追问：你是在逗么？没你想的那么复杂吧