VERILOG中IF和CASE 语句的互换问题

module state_machine(A,B,C,rst,clk,Z,W);

input [3:0] A,B,C;
input rst,clk;
output [5:0] Z;
wire [4:0] Y;
reg [5:0] Z;
wire [6:0] Y1,Y2;
output W;
reg W;
reg[1:0] CTRL;

adder adder1(.input1(A),.input2(B),.output1(Y));
adder adder2(.input1(Z),.input2(Y),.output1(Y1));
adder adder3(.input1(Z),.input2(C),.output1(Y2));

always@(posedge clk or negedge rst)
begin
if(rst==0)
begin
Z=6'b000000; //reset all outputs
CTRL <= 2'b00;
end
else
begin

if (CTRL==2'b00)
begin
Z <= 6'b000000;
W <= 1'b0;
CTRL <= CTRL+2'b01;
end

else if (CTRL==2'b01)
begin
Z = Y1;
W <= 1'b0;
CTRL <= CTRL+2'b01;
end

else if (CTRL==2'b10)
begin
Z = Y2;
W <= 1'b0;
if(Z>4*A)
CTRL <= 2'b11;
else
CTRL <= 2'b01;
end

else if(CTRL==2'b11)
begin
W <= 1'b1;
Z = Z;
CTRL <= 2'b11;
end
end
end
endmodule

想问一下如何把上面的IF ELSE语句改成CASE语句？我的程序如下，但是结果不对
module state_machine(A,B,C,rst,clk,Z,W);

input [3:0] A,B,C;
input rst,clk;
output [5:0] Z;
wire [4:0] Y;
reg [5:0] Z;
wire [5:0] Y1,Y2;
output W;
reg W;
reg[1:0] CTRL;

adder adder1(.input1(A),.input2(B),.output1(Y));
adder adder2(.input1(Z),.input2(Y),.output1(Y1));
adder adder3(.input1(Z),.input2(C),.output1(Y2));

always@(posedge clk or negedge rst)
begin
if(rst==0)
begin
Z=6'b000000; //reset all outputs
CTRL <= 2'b00;
end
end

always@(CTRL)
begin
case(CTRL)
2'b00:begin
Z <= 6'b000000;
W <= 1'b0;
CTRL <= CTRL+2'b01;
end

2'b01:begin
Z = Y1;
W <= 1'b0;
CTRL <= CTRL+2'b01;
end

2'b10:begin
Z = Y2;
W <= 1'b0;
if(Z>4*A)
CTRL <= 2'b11;
else
CTRL <= 2'b01;
end

2'b11:begin
W <= 1'b1;
Z = Z;
CTRL <= 2'b11;
end

default: begin
Z=6'b000000;
CTRL <= 2'b00;
end

endcase
end

endmodule

基本的语法都不通，非阻塞赋值是综合成寄存器的，需要在时钟的沿触发，不能写成组合逻辑。

另外每一个信号单独成块，不要合在一起写，难以定位

always @(en or din) if(en) case(din) 8'b

always@(posedge clk or negedge rst) begin if(rst==0) begin Z=6'b000000; //reset all outputs CTRL <= 2'b00; end else case(CTRL) 2'b00:begin Z <= 6'b000000; W <= 1'b0; CTRL <= CTRL+2'b01; end 2'b01:begin Z = Y1; W <= 1'b0; CTRL <= CTRL+2'b01; end 2'b10:begin Z = Y2; W <= 1'b0; if(Z>4*A) CTRL <= 2'b11; else CTRL <= 2'b01; end 2'b11:begin W <= 1'b1; Z = Z; CTRL <= 2'b11; end default: begin Z=6'b000000; CTRL <= 2'b00; end end endcase 我也是初学者，不知道这样行不行。 另外楼上说：“另外每一个信号单独成块，不要合在一起写，难以定位”具体什么意思，能详细说说吗