mux16_1选择器的VHDL程序

mux16_1选择器的VHDL程序

use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity mux16_1 is
port(s3,s2,s1,s0:in std_logic;
a15,a14,a13,a12,a11,a10,a9:in std_logic;
a8,a7,a6,a5,a4,a3,a2,a1,a0:in std_logic;
ena:in std_logic;
y:out std_logic);
end mux16_1;
architecture a of mux16_1 is
signal s:std_logic_vector(3 downto 0);
begin
s<=s3&s2&s1&s0;
y<=a0 when s="0000"else
y<=a0 when s="0000"else
a1 when s="0001"else
a2 when s="0010"else
a3 when s="0011"else
a4 when s="0100"else
a5 when s="0101"else
a6 when s="0110"else
a7 when s="0111"else
a8 when s="1000"else
a9 when s="1001"else
a10 when s="1010"else
a11 when s="1011"else
a12 when s="1100"else
a13 when s="1101"else
a14 when s="1110"else
a15 ;
end a;