请问用ISE软件用VHDL语言实现一个4位十进制数字显示的数字式频率计的程序应该怎么写?我下面这个有应该这样改?谢谢

请问用ISE软件用VHDL语言实现一个4位十进制数字显示的数字式频率计的程序应该怎么写?我下面这个有应该这样改?谢谢

1）设计任务及要求     设计一个4位十进制数字显示的数字式频率计。要求如下：     a) 4位十进制数字显示的数学式频率计，其频率测量范围为0~9999kHz，测量单位为kHz。     b)当输入的信号大于9999kHz时，输出显示全为H。下面即为采用VHDL语言编写的分频模块设计文件 LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_signed.ALL;USE IEEE.STD_LOGIC_unsigned.ALL;ENTITY frecoj28 IS      PORT(cp1hz: IN       STD_LOGIC;--clock2,clock5input: IN   STD_LOGIC;--clock0reset: IN   STD_LOGIC;show1  :OUT  STD_LOGIC_VECTOR(6 DOWNTO 0);--7digit ledshow2  : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);show3  : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);show4  : OUT STD_LOGIC_VECTOR(6 DOWNTO 0));END frecoj28;ARCHITECTURE a OF frecoj28 ISSignal cp05hz:   STD_LOGIC;Signal divifrecoun:  integer range 0 to 64;Signal overflow_1:   STD_LOGIC;Signal play0_1,play1_1,play2_1,play3_1:   integer range 0 to 9;Signal overlatch_1:   STD_LOGIC;Signal p0latch_1,p1latch_1,p2latch_1,p3latch_1:   integer range 0 to 9;component fretest isport(cp3,input,reset,cp1hz:in  STD_LOGIC;          overflow:out  STD_LOGIC;play0,play1,play2,play3:out  integer range 0 to 9);end component;component frelatch isport(reset:IN  STD_LOGIC;cp3: IN  STD_LOGIC;overflow:IN  STD_LOGIC;play0,play1,play2,play3:in integer range 0 to 9;overlatch :OUT  STD_LOGIC;p0latch,p1latch,p2latch,p3latch:out integer range 0 to 9);end component;component display isport(cp1: IN    STD_LOGIC;overflow: IN   STD_LOGIC;p0,p1,p2,p3:in integer range 0 to 9;show1 : OUT       STD_LOGIC_VECTOR(6 DOWNTO 0);--7digit ledshow2 : OUT       STD_LOGIC_VECTOR(6 DOWNTO 0);show3 : OUT     STD_LOGIC_VECTOR(6 DOWNTO 0);show4 : OUT       STD_LOGIC_VECTOR(6 DOWNTO 0));end component;beginprocess(cp1hz)begin IF (cp1hz'event AND cp1hz='1') THENcp05hz<= not cp05hz;                    -- cp05hz=0.5hzend if;end process;u1:fretest PORT MAP(cp05hz,input,reset,cp1hz,overflow_1,play0_1,play1_1,play2_1,play3_1);u2:frelatch PORT MAP(reset,cp05hz,overflow_1,play0_1,play1_1,play2_1,play3_1,                     overlatch_1,p0latch_1,p1latch_1,p2latch_1,p3latch_1);u3:display PORT MAP(cp05hz,overlatch_1,p0latch_1,p1latch_1,p2latch_1,p3latch_1,                    show1,show2,show3,show4);end a;  --*******************underlays:  --testLIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_signed.ALL;ENTITY fretest IS         PORT(cp3: IN    STD_LOGIC;input: IN      STD_LOGIC;reset: IN      STD_LOGIC;cp1hz: IN   STD_LOGIC;overflow: OUT  STD_LOGIC;     play0,play1,play2,play3:   out integer range 0 to 9);    END fretest;ARCHITECTURE b OF fretest ISSignal clear: STD_LOGIC;beginprocess(input,reset,clear)variable r0,r1,r2,r3:   integer range 0 to 9;beginclear<=((not cp1hz )and (not cp3));    IF(reset='1' or clear='1') THENoverflow<='0'; r0:=0;r1:=0;r2:=0;r3:=0;  elsif cp3='0' then   r0:= r0;r1:= r1;r2:= r2;r3:= r3;elsif (input'event AND input='1') THENif r0=9 and r1=9 and r2=9 and r3=9 THENoverflow<='1';r0:=0;r1:=0; r2:=0;r3:=0;elsif r0=9 and r1=9 and r2=9 and r3<9 THENr3:=r3+1; r0:=0;r1:=0; r2:=0; elsif r0=9 and r1=9 and r2<9  THEN r2:=r2+1;r0:=0;r1:=0; elsif r0=9 and r1<9 THENr1:=r1+1;r0:=0; elsif r0<9  THEN   r0:=r0+1;                              end if;end if;play0<=r0;play1<=r1;play2<=r2;play3<=r3;end process;end b;  --latchLIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_unsigned.ALL;ENTITY frelatch IS     PORT(reset: IN STD_LOGIC;cp3: IN STD_LOGIC;overflow: IN STD_LOGIC;play0,play1,play2,play3:   in integer range 0 to 9;overlatch: out       STD_LOGIC;p0latch,p1latch,p2latch,p3latch: out  integer range 0 to 9);END frelatch;ARCHITECTURE b OF frelatch ISbeginprocess(cp3,reset)beginif reset='1'thenoverlatch<='0'; p0latch<=0;p1latch<=0;p2latch<=0;p3latch<=0;elsif (cp3'event AND cp3='0')THEN      overlatch<=overflow;p0latch<=play0;p1latch<=play1;p2latch<=play2;p3latch<=play3;end if;end process;end b;  --displayLIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_signed.ALL;ENTITY display IS      PORT(cp1:IN  STD_LOGIC;overflow:IN  STD_LOGIC;p0,p1,p2,p3:in integer range 0 to 9;show1   : OUT      STD_LOGIC_VECTOR(6 DOWNTO 0);--7digit ledshow2    : OUT    STD_LOGIC_VECTOR(6 DOWNTO 0);show3    : OUT    STD_LOGIC_VECTOR(6 DOWNTO 0);show4    : OUT    STD_LOGIC_VECTOR(6 DOWNTO 0));END display;ARCHITECTURE b OF display ISbegin    process(p0,p1,p2,p3)begin if(overflow='1')thenshow1<="0110111";show2<="0110111";show3<="0110111";show4<="0110111";elsecase p0 is         --显示的数字      when 0 => show1<="1111110";when 1 => show1<="0110000";when 2 => show1<="1101101";when 3 => show1<="1111001";when 4 => show1<="0110011";when 5 => show1<="1011011";when 6 => show1<="0011111";when 7 => show1<="1110000";when 8 => show1<="1111111";when 9 => show1<="1110011";      when others=> show1<="0000000";end case;case p1 is         --显示的数字      when 0 => show2<="1111110";when 1 => show2<="0110000";when 2 => show2<="1101101";when 3 => show2<="1111001";when 4 => show2<="0110011";when 5 => show2<="1011011";when 6 => show2<="0011111";when 7 => show2<="1110000";when 8 => show2<="1111111";when 9 => show2<="1110011";      when others=> show2<="0000000";end case;case p2 is         --显示的数字      when 0 => show3<="1111110";when 1 => show3<="0110000";when 2 => show3<="1101101";when 3 => show3<="1111001";when 4 => show3<="0110011";when 5 => show3<="1011011";when 6 => show3<="0011111";when 7 => show3<="1110000";when 8 => show3<="1111111";when 9 => show3<="1110011";      when others=> show3<="0000000";end case; case p3 is         --显示的数字      when 0 => show4<="1111110";when 1 => show4<="0110000";when 2 => show4<="1101101";when 3 => show4<="1111001";when 4 => show4<="0110011";when 5 => show4<="1011011";when 6 => show4<="0011111";when 7 => show4<="1110000";when 8 => show4<="1111111";when 9 => show4<="1110011";      when others=> show4<="0000000";end case;end if;end process; end b;