谁给做个30进制加法计数器，要程序。VHDL语言的。

谁给做个30进制加法计数器，要程序。VHDL语言的。

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
LIBRARY lpm;
USE lpm.lpm_components.all;

entity counter is
port (
clk : in std_logic;
counter_out : out std_logic

);
end counter;

architecture coun_30 of counter is

signal counter_temp : std_logic;
signal num : std_logic_vector(4 downto 0);

begin
count_gen:component LPM_COUNTER
GENERIC MAP(LPM_WIDTH =>5,LPM_MODULUS=>30)
PORT MAP (clock=>clk,
q=>num,
aclr=>'0');
counter_temp_gen:process(clk,num)
begin
IF (clk'EVENT AND clk='1') THEN
if num="00000" then
counter_temp<='1';
ELSE
counter_temp<='0';
END IF;
end if ;
END PROCESS;

counter_out<=counter_temp;

end architecture coun_30;

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity cnt16 is port ( clk : in std_logic; rst: in std_logic; en: in std_logic; cout : out std_logic ); end cnt16; architecture behav of cnt16 is signal bcd :std_logic_vector(3 downto 0); begin process(clk, rst, en) variable cqi : std_logic_vector(3 downto 0); begin if rst = '1' then cqi := (others =>'0') ; elsif clk'event and clk='1' then if en = '1' then if cqi = "